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1 Codec Principle of ADV212 Figure 1 shows the function diagram of ADV212, which is mainly composed of pixel interface, wavelet transform engine, entropy encoder/decoder, embedded RISC processor, memory system and internal and external DMA. The basic flow of operation is that the video or pixel data is input through the ADV212 pixel interface, and the effective sample values ​​are transmitted to the wavelet transform engine through interlaced scanning (the wavelet transform engine can perform up to 6 levels of wavelet decomposition on the code block). The data entering the wavelet transform engine is divided into tiles or frames, and each tile or frame is decomposed into a number of subbands by a 5/3 fixed point operation or a 9/7 floating point operation filter, and corresponding wavelet coefficients are generated, and then Write to internal registers. Three entropy encoders/decoders are used to perform background modeling and arithmetic coding on the coding blocks of wavelet coefficients, and calculate the optimal rate and distortion during compression. The data stream of the JPEG2000 standard formed by entropy coding is stored in the code FIFO. The code FIFO primarily buffers the internal high speed bus and the low speed host interface. Code stream data can be shared by a read-write access protocol ( 
, ADDR) Output from the host interface, or external DMA engine output coordinated by the external DMA controller through the DREQ/DACK protocol. The internal DMA engine performs high bandwidth, high performance transfers between memories and between modules and memories. The RISC processor has a ROM and RAM corresponding to each program and data memory, interrupt controller, standard bus interface, and timer counter. 
2 system hardware design This program as a high-definition video data compression system, first of all from the system to achieve functional and cost-effective considerations, using FPGA + ADV212 to achieve.
Video decoder selection: The video decoder uses the ADV7402 HD video decoder. It features a 10-bit ADC, 12 analog inputs, standard definition (480i, NTSC, PAL, SECAM), HD (1080i, 720p) and graphics RGB input (1 280xl 024@60 Hz) for seamless connection to the ADV212.
ADV212 chip count: 1 10 bit high definition (HDTV) video signal, input data transmission rate is about 124 Ms / s, and ADV212 pixel interface input rate limit, 65 MS / s in irreversible mode, reversible mode The bottom is 32 MS/s. This requires the system to be composed of at least two ADV212s. The system selects two ADV212 compression devices, and the YCbCr data is used in the 4:2:2 format to complete the data compression processing of luminance (Y) and chrominance (CbCr) respectively. The data usage is the EAV/SAV encoding format. Figure 2 shows the block diagram of the system structure. The solution includes a video capture and decoding module, a video image JEPG200 compression module, a compression merge module, a logic control module, and a communication output module. 
FPGA selection: Altera's Cyclone III series EP3C55F484C8 device with 328 user I/O, 55 856 available logic elements, 312 embedded multiplier units and 4 phase-locked loops for easy initialization and compression of ADV212 Capture and combine the brightness compression data with the chroma compression data.
3 ADV212 device initialization process and parameter configuration
3.1 ADV212 Initialization Flow The ADV212 initialization routine is configured by configuring the ADV212 internal direct registers and indirect registers according to specific instruction commands. Figure 3 shows the initialization process of the ADV212 code. The initialization program starts with the access of the direct registers such as the PLL register, the BOOT register, the MMODE register, and the BUSMODE register. When accessing the direct register, the target system must maintain the input pin ADDR. , and the state of HDATA (write). When the firmware and configuration parameters are loaded, the software restarts and then configures the BUSMODE and MMODE registers and the application special registers again. Next, make sure the correct firmware is loaded by the application ID. The correct firmware load can be verified by the interrupt or voting procedure of the EIRQFLG register. When you are sure that the firmware connection is loaded and the EIRQFLG register is cleared. The coding begins.
3.2 ADV212 Parameter Configuration Clock Configuration: HD video 1080i requires VCLK to be 74.25 MHz. According to the ADV212 data sheet, JCLK must be at least 2VCLK, so the maximum pulse frequency is recommended to be 0.35J-CLK, which is close to 50 MHz, which is the maximum read and write pulse frequency.
Bus and DMA configuration: HDTV (1080i) application, 2 ADV212 must work in irreversible maximum transfer rate of 65 MS / s mode, video input takes 32-bit VDATA bus (pixel interface), compressed data output takes 2 ADV212 share 32 Bit HDATA bus (host interface). The ADV212 is initialized to select attribute type 5 (ATTRTYPE), the attribute data is read using the single-transmission DREQ/DACK DMA mode, and the code stream reading adopts the pulse transmission DREQ/DACK DMA mode. 
As shown in Figure 3. Set the ADV212 internal clock, bus mode, indirect register access mode, etc. according to the direct register configuration of the ADV212. The initialization process of ADV212_l and ADV212_2 is as follows: PLL_HIOx008h, PLL_HO, 0x0084: Set VCLK to 74.25 MHz; BOOT: 0x008A boot mode is used for loading on that; BUSMODE: 0x000A sets the host control data width and DMA data width to 32 bits; MMODE: 0x000A sets the number of indirect data access bits and the indirect address step size to 32 bits; IADDR: Ox00050000 sets the starting point for program storage; IDATA: 0x******** in the program memory loader; BOOT Ox008D software Restart; BUSMODE0x000A resets the host control data width and DMA data width to 32 bits: MMODE 0x000A resets the indirect data access bits and the indirect address step size to 32 bits. The parameters of ADV212 are set according to IADDR and IDATA. The parameter configuration description is as follows: IADDR 0x00057F00 ADV212_1 and ADV212_2 encoding parameter start address; IDATA 0x02010503 (ADV212_1), 0x03010503 (ADV212_2) 02=1080i brightness (03=1080i chromaticity); 0l= 10-bit precision; 05=5-level wavelet transform; 03=Y, C single-level; IDATA 0x03000000 03=code block size is 128x32; 00=irreversible 9x7 wavelet; 00=skip no byte area; 00=no attribute data output ; IDATA0x01019500 (ADV212_1), 0x01008700 (ADV212_2) Ol = target video domain, frame size; 019500 = 10: 1 compression ratio (008700 = 30: 1 compression ratio); IDATA 0x00000001 00 = LRCP series format; 00 = EAV. SAV encoding, all cathodes synchronized; 00=Qfaetor is 1X; 01=encoding format is. J2c; IDATA0x00000000 saves the parameters.
After the above configuration, EIRQFLG (address Ox6h) of ADV212_1 and ADV212_2 is written to 0x0400 to clear the software interrupt (SEIRQ0) and start the program. When DREQ0 becomes valid, ADV2-12 is ready to transfer data from CODE FIFO. The host follows the specific timing of ADV212. Start data transfer.
4 FPGA structure function Figure 4 is the internal logic of the FPGA. The FPGA is mainly composed of the following functional modules: 1) Host logic, based on the Nios embedded host logic module, mainly realizes the read and write operations of two ADV212, realizes the initialization of ADV212 and Firmware download; 2) ADV212 arbitration logic, realizes two ADV212 compressed data synchronization, responds to the bus to judge the state of the response signal function; 3) Y/C merge logic, which realizes the brightness compression data according to the read attribute and code information The chrominance compression data merge function; 4) The data buffer control module buffers the external DMA channel read rate and the luminance/chrominance merge data flow between the logic modules. 
In the FPGA main control module, to ensure that the ADV212 is loaded with the correct firmware, it is implemented in four steps: The first step is to write 0x0400 to the external interrupt enable register to mask the software interrupt 0 bit: Step 2 Wait until the interrupt Pin IRQ is pulled low. Step 3 Check if the EIRQFlLG[10] bit of the external interrupt flag register is set. Step 4 reads the application identifier from the software tag register. If it reads 0XFF82, the firmware is loaded correctly. The system can start working.
When the system starts working, the FPGA is arbitrating. The control module analyzes and judges the number of partition bytes read from the ADV212 attribute FIFO. The data buffer control module registers the compressed data read in the ADV212 code FIFO. The arbitration/control module analyzes the results to control the luminance/chrominance combining logic module. The code stream is interleaved from the Y data starting from the opposite parts of the two devices (Y and CbCr), and output to the buffer and then output by the communication port.
5 Conclusion The high-definition video compression system based on FPGA+ADV212 structure can realize real-time processing of high-definition video (YCbCr 4:2:2 format) signal. The system has the advantages of high cost performance, good reliability, flexible adjustment and easy recovery of compressed signals. However, the system uses an irreversible 9/7 wavelet transform, and the video processing has a certain distortion. In order to obtain 1080i video signals with better characteristics (such as lossless compression), it is recommended to use 3 or more ADV212s to process signals. The signal format can be in YCbCr 4:4:4 format. With the wide application of JPEG2000, the dedicated image compression device ADV212 will be more and more applied to the field of video and image compression.
Design of HD Video Compression System Based on ADV212
With the increase of the amount of social information, people are increasingly demanding multimedia video compression. High-definition video compression with high compression and low bit rate has been widely used in household appliances, medical equipment, military reconnaissance, satellite remote sensing and other fields. . ADI's new ADV212 is a device with real-time compression/decompression standard (SD) video signals and high definition (HDTV) video signals. It has the advantages of high reliability, flexible configuration, and support for video formats. Data processing in multiple video formats. This paper introduces the design of the ADV212 HD video compression system, which supports SMPTE274M (1080i) video real-time encoding.